1. Technical Field
The present invention relates to a semiconductor memory apparatus, and in particular, to an apparatus and a method for outputting data of a semiconductor memory apparatus.
2. Related Art
FIG. 1 shows an apparatus for outputting data of a semiconductor memory apparatus according to the related art. Referring to FIG. 1, the data outputting apparatus comprises a predriver 10 and a main driver 20. The predriver 10 includes a pull-up circuit 11 that controls a slew rate due to pulling-up of input data and a pull-down circuit 12 that controls a slew rate due to pulling-down of input data, and the main driver 20 includes transistors P1 and N1 connected between a power terminal and a ground terminal.
The pull-up circuit 11 and the pull-down circuit 12 have the same structure. In detail, as shown in FIG. 2, the pull-up circuit 11 and the pull-down circuit 12 have an inverter structure in which transistors P2 and N2 are connected between a power terminal and a ground terminal, and a resistor R10 is connected to an output terminal.
The operation of the above-mentioned related art will be described.
When data is input to the predriver 10, an up-signal and a down signal each having a predetermined gradient are output by the pull-up circuit 11 and the pull-down circuit 12 of the predriver 10.
In this state, when the data is shifted from a high level to a low level, an off-delay of the transistor P1 of the main driver 20 is controlled by raising the level of the up-signal, and an on-delay of the transistor N1 of the main driver 20 is controlled by lowering the level of the down-signal of the transistor N1.
In contrast, when the data is shifted from a low level to a high level, an on-delay of the transistor P1 of the main driver 20 is controlled by lowering the level of the up-signal, and an off-delay of the transistor N1 of the main driver 20 is controlled by raising the level of the down signal.
The pull-up slew rate and the pull-down slew rate are controlled as described above.
However, according to the related art, a rising delay and a falling delay of the up signal and the down signal, which are the main parameters for controlling the slew rate are determined by the resistor R10 and turn on-resistances of the transistors P2 and N2.
Therefore, the data outputting apparatus of a semiconductor memory apparatus has the following problems.
It is not applicable for a system that requires a high speed operation because the slew rate is fixed by the resistor and the turn on-resistance of the transistors such that the slew rate cannot be varied.
Further, the applicable range is excessively limited due to the fixed slew rate and the fixed data output timing.